Regviz

Espressif Systems /ESP32 /TIMG0 /INT_CLR_TIMERS

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as INT_CLR_TIMERS

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Espressif Systems/ESP32/TIMG0/INT_CLR_TIMERS#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (T0_INT_CLR)T0_INT_CLR 0 (T1_INT_CLR)T1_INT_CLR 0 (WDT_INT_CLR)WDT_INT_CLR 0 (LACT_INT_CLR)LACT_INT_CLR

Fields

T0_INT_CLR

interrupt when timer0 alarm
T1_INT_CLR

interrupt when timer1 alarm
WDT_INT_CLR

Interrupt when an interrupt stage timeout
LACT_INT_CLR

Links

()

Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data